Analog/digital converters of this type are known from U.S. Pat. Nos. 3,765,012, 4,361,831, and 5,262,780.
A circuit diagram of this so-called multiple ramp procedure is depicted in FIG. 1. In addition, FIG. 2 depicts the time trace of the voltage V.sub.C at the integration capacitor C and/or at the output 11 of the integrator 1, for explaining the method of operation.
The current I.sub.x to be measured is continuously supplied to the input 10 of the integrator 1. If the analog/digital converter is used as a voltage meter, the measurement voltage is converted via a fixed resistor into a measurement current I.sub.x. At certain times, the switch 3 is closed and the input 10 of the integrator 1 is additionally supplied with a fixed reference current I.sub.ref of polarity opposite that of I.sub.x. The reference current I.sub.ref can, for example, be produced from a Zener diode (=reference voltage) and a fixed resistor. For illustrating the temporal sequence in FIG. 2, it is assumed that I.sub.x is negative and I.sub.ref is positive. Starting from a voltage level zero at the integration capacitor C at time t.sub.1 in FIG. 2, the switch 3 is open during the period T.sub.1, and the voltage V.sub.C at the output 11 of the integrator 1 increases proportionally to I.sub.x. After the time T.sub.1, this voltage reaches the value: ##EQU1##
At time t.sub.2 in FIG. 2, the switch 3 is closed. Since I.sub.ref &gt;-I.sub.x, the influence of I.sub.ref now predominates, and the voltage V.sub.C falls until it reaches the value zero again at time t.sub.3. The following equation then applies for the charge balance: ##EQU2##
After appropriate transformation, one obtains: ##EQU3##
If T.sub.1 +T.sub.2 =T=constant and I.sub.ref =constant, then T.sub.2 is directly proportional to the current I.sub.x to be measured.
In the circuit of FIG. 1, the switch 3 is driven by a bistable element 4 which closes the switch 3 in its "on" condition and opens the switch 3 in its "off" condition. The switching to the "on" position at the times t.sub.0, t.sub.2, t.sub.4 etc. in FIG. 2 results from the overflow signal of a time counter 6 on the line 12. The time counter 6 continuously counts the pulses of a pulse generator 5, so that the overflow signal appears at regular time intervals. This allows the condition T.sub.1 +T.sub.2 =T=constant to be realized. The switching of the bistable element 4 back into the "off" condition at the times t.sub.1, t.sub.3 etc. in FIG. 2 results from the output signal of the comparator 2 (line 13) upon reaching the zero line of the integrator voltage at point 11 in FIG. 1. If the switch 3 is closed, a gate 8 is opened via a line 14, so that, during the time T.sub.2, the pulses of the pulse generator 5 are registered in a result counter 7. This pulse count proportional to T.sub.2 is thereby, according to equation (3), also proportional to the current I.sub.x to be measured, since T and I.sub.ref are constant. The microprocessor 9 in FIG. 1 also receives the comparator signal via line 15. Following the next pulse of the pulse generator (which is simultaneously the clock unit for the microprocessor 9 in FIG. 1), the microprocessor can read out the value of the result counter 7 and output and/or further process this value as the measurement result of a single measurement cycle. The result counter 7 is reset to zero via the line 16 at the times t.sub.0, t.sub.2, t.sub.4 etc.
In the circuit of FIG. 1, it is further provided that the opening of the switch 3 does not occur in synchronization with the comparator signal on the line 13, but only with the next pulse of the pulse generator 5 (synchronization input 60 on the bistable element 4). The equation (2) thereby is only approximate for each measurement cycle. However, the small deviations are transferred in analog form to the next measurement cycle, so that this error cancels out over several measurement cycles. Switching in synchronization with the pulse of the pulse generator 5 has the great advantage that T.sub.1 as well as T.sub.2 are always exact multiples of the clock period of the pulse generator 5, so that no rounding errors can add up during the adding/averaging of several measurement cycles. A total result with N-fold resolution results from the sum--or the running sum--and/or the average of N measurement cycles. The practical resolution is limited only by the quality of the components used.
The multiple ramp process is described only briefly in the preceding passages. Particulars can be found in the patent specifications already cited.
Advantages of this process include:
The current I.sub.x is not switched; therefore there is no influence from current/voltage-dependent switching capacities of the switch; PA1 The size of the integration capacitor C does not enter into the calculated result, as evident from equation (3); PA1 Through averaging and/or summation over N measurement cycles, the resolution of the analog/digital converter can be increased in correlation to the number N; PA1 The measurement results are available in a fixed time slot pattern, so that further averaging, calculation of rates of change, etc., are made easier.
This known process has the disadvantage, however, that after a change in current I.sub.x at the input, the pulses summed in the result counter only gradually converge to the correct final value and do not converge at all for values of .vertline.I.sub.x /I.sub.ref.vertline.&gt;1/2.
This is to be explained in greater detail with reference to FIG. 3. Several sequential up-integrations and down-integrations are depicted here, just as in FIG. 2. The theoretical voltage trace at the capacitor C (in FIG. 1) in steady state condition is indicated with a dashed line; the actual voltage trace which occurs, for example, after a disturbance or after a sudden voltage change at the input (in which case the down-integration at time t.sub.0 starts with a value which deviates from the steady state condition by a value x.sub.0) is indicated with a solid line. The time error that thereby arises in the first down-integration is s.sub.1, the time error arising in the second down-integration is s.sub.2, etc.
Due to the parallel relationship of the two straight lines 17 and 18, one obtains, from the intercept theorems: ##EQU4##
And, analogously, due to the parallel relationship of the two straight lines 19 and 20: ##EQU5##
By elimination of V.sub.0, one thus obtains: ##EQU6##
If one considers that s.sub.2 and s.sub.1 have different signs and one generalizes equation (6) to the error s.sub.n, one obtains: ##EQU7##
One recognizes from this that, after a disturbance, the time error s.sub.n decays exponentially as long as T.sub.2 &lt;T.sub.1.
The time ratio T.sub.2 /(T.sub.1 +T.sub.2) in the equation (3) must therefore be smaller than 0.5 in order for the disturbance to die out. For T.sub.2 &gt;T.sub.1 and/or T.sub.2 /(T.sub.1 +T.sub.2)&gt;0.5, the time error s.sub.n increases with each measurement cycle, and the procedure thus diverges.
The time T.sub.2, during which the bistable element 4 in FIG. 1 is in its "on" condition and in which the result counter 7 adds up the pulses of the pulse generator 5, must therefore remain restricted to values clearly under 0.5.multidot.(T.sub.1 +T.sub.2). This restricted counting time for the result counter 7--restricted to under 50% of the total time--requires a pulse generator that is twice as fast in order to attain a predetermined resolution within a predetermined amount of time. Even if a single measurement period is made only approximately 10 ms long, the gradual convergence leads to a relatively long time to determine the measurement result, particularly when compared with the standard dual slope process, in which the final measurement result is available after only one up-integration and one down-integration.
It has already been attempted (U.S. Pat. No. 5,066,955) to improve the transient behavior of the system and to utilize the entire measurement time as counting time as well. This attempt has involved supplying quantities of charge periodically to the input of the integrator via capacitors. As the result of the capacitive coupling, the DC voltage component of these additional quantities of charge is, on average, zero, so that they have no influence on the measured value. However, the circuitry expenditure is significant and, in addition, non-ideal behavior of the additional capacitors leads to measurement errors.
In U.S. Pat. No. 5,262,780, the multiple ramp process is modified in that the total measurement time, which (in the context of that invention) extends from a first zero-crossing of the comparator over the duration of N measurement cycles to a further zero crossing of the comparator, is adjusted to the cycle duration of a dominant interfering frequency--generally the power-line frequency. This adjustment is accomplished, in particular, by displacement of the switch-on time of the bistable element in the last measurement cycle. The thereby resulting disturbance of the steady state trace of the integrator voltage must be corrected again at the beginning of the next complete measurement period. This procedure has the disadvantage that only measurements with very low conversion frequencies can be performed. In the case of interfering frequencies that are not captured by the cycle duration of the complete measurement period, this leads to aliasing errors for interfering frequencies greater than 1/(2.multidot.N.multidot.T). In the case of changes in the current I.sub.x to be converted, the time for up to N measurement cycles can, in unfavorable situations, be lost before correct measurement begins.
A further disadvantage of the prior art cited is the high demands which the capacitor C of the integrator 1 has to satisfy. For different input currents I.sub.x at the analog/digital converter, different average DC voltage components occur at the integration capacitor C, because the switching points t.sub.1, t.sub.3 etc., in FIG. 2 are fixed at zero volts and the voltage at the other switching points at t.sub.0, t.sub.2, t.sub.4 etc., changes depending on the value of I.sub.x. This leads to hysteresis effects in many capacitor dielectrics and to a change in the capacitance, and thereby to hysteresis and linearity errors, in the analog/digital converter.